Микросхема SN74HC138N, Дешифратор/декодер [PDIP-16]

Характеристики

SN74HC138N, Дешифратор/декодер [PDIP-16]The SN74HC138N is a 3-line to 8-line Decoder/Demultiplexer, designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

• Targeted Specifically for High-speed Memory Decoders and Data-transmission Systems
• Outputs Can Drive up to 10 LSTTL Loads
• Low-power Consumption, 80µA Maximum ICC
• 15ns Typical Propagation Delay Time
• ±4mA Output Drive at 5V
• Low Input Current of 1µA Maximum
• Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception